Wavecom GS64 Spécifications télécharger pdf (Page 37)

Product Technical Specification & Customer Design Guidelines

Interfaces

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WA_DEV_Q64_PTS_001-003 January 9, 2009

3.6.3 Application

The level shifter must be set at 2.8V compliant with a V28 electrical signal.

Figure 5: Example of RS-232 level shifter implementation for UART1

U1 chip also protects the Q64 against ESD at 15KV. (Air Discharge).

Recommended components:

 R1, R2 : 15KΩ

 C1, C2, C3, C4, C5 : 1uF

 C6 : 100nF

 C7 : 6.8uF TANTAL 10V CP32136 AVX

 U1 : ADM3307EACP ANALOG DEVICES

 J1 : SUB-D9 female

R1 and R2 are necessary only during Reset state to lift RI and DCD1 signals to high

level.

The ADM3307EACP chip is able to reach 921Kb/s*. If other level shifters are used,

make sure that their speeds are compliant with the UART1 speed.

*: For this baud rate, the power supply must be provided by an external regulator at

3.0 V.

The ADM3307EACP can be powered by an external regulator at 2.8 V (the baud rate

will be limited up to 720kbps).

If the UART1 interface is connected directly to a host processor, it is not necessary to

use level shifters. The interface can be connected as shown below:

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Wavecom GS64 Spécifications Page 37